library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ViterbiDecoder is
port(
clk : in std_logic;
rst : in std_logic;
input_data : in std_logic_vector(63 downto 0);
output_data : out std_logic_vector(63 downto 0)
);
end ViterbiDecoder;

architecture Behavioral of ViterbiDecoder is
— Constraint length
constant K : integer := 7;
— Number of states for constraint length 7
constant N : integer := 2**(K-1);

— Generator polynomials
type t_polynomials is array(0 to 5) of std_logic_vector(6 downto 0);
constant polynomials : t_polynomials := (
"1111101", — 0O175
"1111001", — 0O171
"1101001", — 0O151
"1011011", — 0O133
"1010111", — 0O127
"1001111" — 0O117
);

— Branch metric array
type t_branch_metrics is array(0 to 63)